1. Field of the Invention
The present invention relates to a motion vector detection apparatus and, more particularly, to an apparatus for detecting motions between image frames continuously inputted, to calculate a motion vector in terms of pixel block.
2. Discussion of Related Art
In a computer vision field such as inspection and instrumentation, generally, motion vector calculation is required to detect where a reference model image is located in a frame to be detected. Security and supervision systems also need motion vector calculation to check if there is variation between image frames recorded at regular intervals. The computer vision field of inspection and instrumentation and security and supervision systems employ MPEG as a picture compression standard which uses a coding method according to motion correction between frames. This requires faster motion vector arithmetic.
The detection of the motion vector requires the existence of a reference picture frame and frame to be detected. The motion vector is a vector value representing that which picture data in the frame to be detected closely coincides with picture data in the reference picture frame. One motion vector is obtained for each pixel block in a specific size. The expression for calculating the motion vector is described below. ##EQU1##
In this expression, letting r(i,j) be pixel data in the reference picture frame, s(i,j) be pixel data in the frame to be detected, N.times.N be the size of pixel block whose motion vector is required, and (x,y) be the motion vector, when expression (1) is conducted for every location of (x,y) in a detection region, (x,y) which minimizes D(x,y) is determined as the motion vector. The calculation of the motion vector needs a large amount of operations. For this, a high-speed digital signal processor or exclusive hardware is used. With the high-speed digital processor, its algorithm is easy to change but its processing speed is limited, so that it cannot be used in real-time picture compression. The exclusive hardware employs a structure in which processing units are connected in parallel as shown in FIG. 1, to increase the processing speed. However, the configuration of each processing unit is so complicated, as shown in FIG. 2, that it is practically difficult to integrate a large number of processing units in a single chip.
Referring to FIG. 1, the conventional motion vector detection apparatus includes: a first frame memory 10 for receiving value R of reference pixel and value S of pixel to be detected, and temporarily storing them; a plurality of processing units 20, connected to the output terminal of first frame memory 10 in parallel, for receiving data outputted from first frame memory 10 and calculating motion vectors; and a minimum value detector 30, connected to the output terminal of processing units 20, for receiving data outputted from processing units 20 and detecting its minimum value.
Referring to FIG. 2, each processing unit 20 includes; a subtractor 20-1 for receiving value R of reference pixel and value S of pixel to be detected, and performing subtraction for them; a first delay 20-2 for delaying value S of pixel to be detected by a predetermined cycle; a second delay 20-3, connected to the output terminal of subtractor 20-1, for receiving data outputted from subtractor 20-1 and delaying it by a predetermined cycle; an absolute value evaluation section 20-4, connected to the output terminal of second delay 20-3, for receiving data outputted from second delay 20-3 and conducting absolute value evaluation; a third delay 20-5, connected to the output terminal of absolute value evaluation section 20-4, for receiving data outputted from absolute value evaluation section 20-4 and delaying it by a predetermined cycle; an adder 20-6, connected to the output terminal of third delay 20-5, for receiving data outputted therefrom and performing addition for it; and a fourth delay 20-7, connected to the output terminal of adder 20-6, for receiving data outputted therefrom and delaying it by a predetermined cycle.
In processing unit 20 of the aforementioned conventional motion vector detection apparatus, when value R of reference 8-bit pixel and value S of pixel to be detected enter to subtractor 20-1 at specific intervals, subtractor 20-1 performs subtraction for data received, and second delay 20-3 delays data outputted from subtractor 20-1. The delayed data is sent to absolute value evaluation section 20-4, and simultaneously, value R of new reference pixel and value S of new pixel to be detected are applied to subtractor 20-1. The delayed data passes through absolute value evaluation section 20-4, is delayed by third delay 20-5, is sent to adder 20-6, and simultaneously, the new value R of reference pixel and new value S of pixel to be detected, which are delayed by second delay 20-3, are applied to absolute value evaluation section 20-4. Through this process, calculations for three values R of reference pixel and values S of pixel to be detected are simultaneously carried out in one processing unit 20.
The addition result in one processing unit 20 is applied to neighboring processing unit 20 such that cumulative addition of the resultant values is carried out. The pixel value in the region to be detected is applied to subtractor 20-1, and at the same time, time-delayed through first delay 20-2, to be sent to neighboring processing unit 20. By doing so, it is possible to obtain an effect of moving the detection location. In the detection of motion vector using the above-described conventional motion vector detection apparatus, the processing units connected in parallel (shown in FIG. 1) are employed to increase the processing speed. However, the configuration of each processing unit (shown in FIG. 2) is so complicated that it is difficult for a large number of processing units to be integrated in a single chip.
Another apparatus for detecting a motion vector is disclosed in U.S. Pat. No. 5,157,732. This apparatus includes characteristic image memory means for storing an image signal for detecting a motion vector, image motion vector detection means for detecting an image motion vector from the image signal, reliability judgement means for judging the reliability of the detected motion vector, and signal processing means for processing the motion vector signal of the image signal according to the detected motion vector and reliability judgement result.
With this motion vector detection apparatus, the motion vector detected by the vector detection means is judged by the reliability judgement means if it is a correct motion vector, and then processed by the signal processing means, thereby detecting more accurate motion vector. That is, it is judged if the detected motion vector is for unnatural image, or time-delayed, and the motion vector is detected with regard to this judged result. However, this motion vector detection apparatus has also complicated configuration because of addition of processing unit such as the reliability judgement means, similar to the aforementioned conventional motion vector detection apparatus.